Design and Characterization of a Low Noise Amplifier - RF and Microwave Electronic

nsnkoduru
Sep 8, 2024
2 min read

Design and Characterization of a Low Noise Amplifier using Cadence.

Low Noise Amplifier

Objectives: The objective of this lab is to Simulating with the Cadence toolset by design a simple low noise amplifier (LNA). We use LNA to amplify extremely low signals without adding much noise but maximize gain and linearity. While designing LNA, we need to maintain the following specified values for desired parameters. My design simulated result is also shown below.

	Specified	Simulated
Frequency	2.4 GHz	2.4GHZ
Current	<10 mA	3 mA
Voltage VDD	1.8 V	1.8 V
S11 (dB)	<-20 dB	-28.158 dB
S21 (dB)	>15 dB	21.448 dB
NF (dB)	<2 dB	1.7828 dB
1dB compression point	<-10 dBm	-20.9928 dBm
IIP3 (dBm)	>-10 dBm	-9.77 dBm

Design Process:

In this design total of 4 kinds of components are needed in my LNA design. That is NMOS, capacitors, inductors, and resistors. Here we will use the minimum length 180nm but set the width to be 110u. To do so, we set the “fingers” to be “11” and the “Finger Width” to be “10u”, then I had a “Total Width” of “110u”. We will need 3 NMOS transistors in total, one as the amplifying device, one as the cascade device and one as the bias. n18 represents the NMOS transistor with a 1.8V power supply.

Simulation results:

After inserting all the design components and make their connection we got the following diagram in the schematic window.

After designing the schematic diagram, we get our symbol by going to “Create” -> “Cellview” -> “From cellview”. Click “OK” if the pin allocation is correct. So I can see a generated symbol of my LNA which is shown bellow.

In this design process we need to create the testbench schematic for the LNA, which is used for the simulation. We create this new schematic in the same way you did before, but this time name it “LNA_testbench”. We set the parameters in the input

and output port and connected the components together using wires and properly label the wires, once you finish, your testbench will be like bellow.

Now I Selected “Launch” -> “ADE L” then to “Analyses” -> “Choose” any desired parameters such as SP or NF (Noise figure) or KF (Stability factor) or 1-dB compression points or IIP3 point in the window that pops up. We can then fin the values we want.

Here after choosing SP (s-parameters) we got S11 value equal to -28.158 dB for my design and is typically it should be <-20 dB. So, it is much better than our desired value.

S12 value is typically <-30dB and we got -41.196 dB which shows a better design.

S21 value is typically >15dB and we got 21.448 dB which shows a better design

Figure: S22

All four S-parameters in the same window would look like

Typical value of noise figure (NF) value is nearly 2dB where we found 1.7828 dB

Stability factor of the LNA can be plotted as below

Typically, 1-dB compression point < -10 dBm where in my simulation I got

-20.9928 dBm So theoretically I got the perfect value for my design.

input port of my testbench, I added a second frequency and set the value of variable “df” where df=2.5MHz. As every thing went correctly, in the qpss (quasi-periodic steady state) analysis window, we got the IIP3 value is -9.77 dBm which indicate the accurate design theoretically.

Discussion:

Power consumption is essential to proper circuit function and different circuits can handle different levels of power. There are two different types of power consumption that should be minimized in a circuit: dynamic and static. Another important strategy to reduce circuit power consumption is to vary the threshold voltage within components. High threshold voltages when a device is on standby or turned off can minimize leakage current, which reduces static power consumption